Semiconductor (integrated circuit) memory devices are widely used in consumer and commercial applications. Typically, a semiconductor memory device such as a Dynamic Random Access Memory (DRAM) device employs a variety of operating voltages, including an external power supply voltage, ground voltage, internal power supply voltage, reference voltage and high voltage. Among these operating voltages, the internal power supply voltage is used to generate an array power supply voltage applied to a memory cell array.
The power supply lines may be arranged in a power-meshed pattern so as to enhance the efficiency of cell power supply in the memory cell array. The layout of the power supply lines or signal lines may become more significant with an increase in the size of the semiconductor memory device.
An example of the layout of power supply lines is disclosed in U.S. Pat. No. 5,867,440 to Hidaka. In Hidaka, power supply lines and grounding lines are arranged on the memory cell array so as to extend in the column direction. Another example of the layout of power supply lines is disclosed in U.S. Pat. No. 6,385,115 to Nakai, which discloses a power supply configuration in a meshed shape arrangement for a sense amplifier circuit.
The reduction of design rules may result in an increased parasitic capacitance of adjacent bit lines in the memory cell array of the semiconductor memory device. Namely, the adjacent bit lines form a parasitic capacitance caused by an insulation layer that is interposed between the adjacent bit lines, and the capacitance generally increases with a decrease in the thickness of the insulation layer. The parasitic capacitance may cause noise to make the data sensing operation of the sense amplifier unstable.
An approach to reducing the parasitic capacitance is a twisted bit line architecture. For example, a twisted bit line structure and a method for making the same is disclosed in U.S. Pat. No. 6,404,664 to Numata. A twisted bit line architecture can have a relatively low parasitic capacitance and less noise caused by the capacitive coupling among the bit line pairs during a sensing operation.